As shown in FIG. 1, a GaN based Light Emitting Diode (LED) generally comprises a buffer layer 11 on a sapphire substrate 10, an n-type GaN layer 12, an InGaN (or GaN) active layer 13, a p-type GaN layer 14, a transparent electrode 15, a dielectric passivation layer 16, an n-based metal electrode 17 and a p-type metal electrode 18. The method of forming a GaN based Light Emitting Diode (LED) comprises the steps of successively crystal growing of the buffer layer 11 on the sapphire substrate 10, the n-type GaN layer 12, the InGaN 9 (or GaN) active layer 13, and the p-type GaN layer 14 according to the Metal Organic Chemical Vapor Deposition (MOCVD) method; partly etching up to the n-type GaN layer 12 in order to form the n-type metal electrode 17; forming the transparent electrode 15; coating the surface with the dielectric passivation layer 16 except the electrode region; and depositing the n-type metal electrode 17 and the p-type metal electrode 18.
FIG. 2 is a cross-section diagram which illustrates the principle of leakage current occurrence for a GaN based optical semiconductor device in the absence of a dielectric passivation layer.
As shown in FIG. 2, the leakage current flows through the surfaces and boundaries when a voltage is applied to the electrode terminals and has significant effects on the performance of the device and sometimes causes destruction of the device.
For the case of GaN based semiconductor devices, boundaries for electrode deposition of a device are formed by Reactive Ion Etching (RIE). At this instance, the boundaries are damaged due to high energy ion bombardments and leakage current occurs along the damaged boundaries. Also, during the breaking or sawing of a device into individual chips after the completion of the process, too much stress exists on the cleavage boundary of the crystal growth layer and generally the boundaries become very rough due to the cleave not coinciding with the crystal faces. A large amount of leakage current flows along these rough boundaries.
Accordingly, at the conventional GaN based semiconductor, as shown on FIG. 1, the leakage current is prevented by coating the surface between the p metal electrode 18 and the n-type GaN 12 layer with the dielectric passivation layer 16.
The dielectric passivation layer 16 cuts off the passage of the leakage current that flows on the boundaries through the semiconductor surface and protects the surface of the device from external damages. This is an essential process in order to protect the device from surface damages and also secure the reliability of the device as well as improving the assembly yield. This process is also a final stage process which requires an extreme caution.
According to a construction method of the conventional dielectric passivation layer, a dielectric passivation layer such as SiO2 or Si3N4 is deposited using the PECVD or Sputtering process after forming a transparent electrode and the n-type & p-type metal electrodes. In this case, generally plasma is used for the deposition instead of a simple CVD method or thermal deposition method each of which has a weak adhesion strength between the dielectric passivation layer and the semiconductor surface. The plasma deposition method can improve the adhesion among the dielectric passivation layer, the metal surface (transparent electrode) and the semiconductor surface.
However, the deposition of a dielectric passivation layer under a plasma environment might cause damage on the performance of the device since RF power and DC bias, which are necessary for formation of plasma, are directly applied to the surface of the semiconductor. Sometimes this damage on the performance of the device might cause an eventual failure of the whole semiconductor process or a remarkable drop of the performance of the device.
Also, since the dielectric passivation layer deposition process is the final process of the device manufacturing, the total yield and performance of the device can be significantly affected by a small process variable. If an optical semiconductor device is to be operated at a high output mode due to high voltage and high current, the light emission efficiency of the device is lowered due to the thermal resistance characteristic (very low thermal resistance) of the dielectric which reduces the amount of thermal emission generated by the InGaN active layer 13.
Especially, in case of the junction-side down method which bonds a metal frame (or submount 19) with the upper face of the device for thermal emission as shown in FIG. 3, an inconsistent device, where the dielectric passivation layer 16 blocks is between the semiconductor device and the metal frame 19, is constructed.
Also, the amount of leakage current on the p-n diode junction boundary is not negligible and this significantly affects the reliability of the device. It is difficult to sufficiently recognize the leakage current at the initial stage since it affects device yield after assembling and a long term reliability. Hence, it is required to fundamentally block the leakage current between the p-type metal electrode and the n-type GaN layer.